1. Field of the Invention
This invention relates to a variable clock dividing circuit capable stably of switching dividing clocks used in a microcomputer.
2. Description of the Prior Art
Many conventional microcomputers, in particular, single-chip microcomputers provided with peripheral circuits, have a built-in variable clock dividing circuit to switch the system clock frequency corresponding to an application being run by the microcomputer. Since the system clock affects the operation of the entire system, the variable clock dividing circuit of such system clock is required to be highly reliable.
A conventional variable clock dividing circuit comprises a plurality of dividers to divide the basic clock by different dividing ratios, and a switching circuit to select and output one of the clocks output from those plurality of dividers according to the dividing ratio setting signal. In such a conventional variable clock dividing circuit, since the output from a divider is continuously sent to the next input terminal of the divider on the next stage, delay at devices constituting a divider delays the change point of the output clock from the divider; the higher the stage of the divider, the larger the delay from the basic clock becomes.
For this reason, when switching from a certain divider clock to another divider clock, the cycle of the output clock immediately after switching changes by the delay of the divider, which might cause the frequency of the output clock to exceed the guaranteed operation frequency immediately after switching. This excess of the guaranteed operation frequency can cause malfunction of the system. This drawback is particularly prominent when the clock with a large dividing ratio is switched to that with a small dividing ratio due to a large delay.